Integrated circuits having channel regions with different ion levels

ABSTRACT

Methods of forming a channel region between isolation regions of an integrated circuit substrate are disclosed. In particular, a mask can be formed on an isolation region that extends onto a portion of the substrate adjacent to the isolation region to provide a shielded portion of the substrate adjacent to the isolation region and an exposed portion of the substrate spaced apart from the isolation region having the shielded portion therebetween. A channel region can be formed in the exposed portion of the substrate. Related integrated circuits are also discussed.

RELATED APPLICATIONS

[0001] This application is a divisional of U.S. application Ser. No.09/891,905, filed Jun. 26, 2001, which claims priority from KoreanApplication No. 2000-35707, filed Jun. 27, 2000, the disclosure of whichis hereby incorporated herein by reference.

FIELD OF THE INVENTION

[0002] The present invention relates to methods of forming integratedcircuits and to integrated circuits in general, and more particularly,to methods of forming integrated circuit memory devices using ionimplantation and to integrated circuits formed using same.

BACKGROUND

[0003] In dynamic random access memories (DRAMs), data can be recordedby storing charge in a capacitor of a memory cell. To keep data recordedin DRAMs, the data may need to be refreshed periodically. Data retentiontime is one of the characteristics used to determine the performance ofDRAMs. One of the factors that influences data retention time isjunction leakage current. Junction leakage current can be produced by anelectric field at a pn junction boundary or by substrate defects in adepletion region. Decreasing the junction leakage current may increasedata retention time and thereby improve the performance of DRAMs.

[0004] As the integration density of DRAMs increases, the size of atransistor included therein may decrease. Decreasing the size of atransistor may decrease the length of a channel region, thereby causingshort channel effects such as a decrease in the threshold voltage V_(T)of the transistor. A doping concentration can be increased graduallyduring channel ion-implantation to compensate for a decrease in V_(T)and thereby adjust V_(T) to a proper level.

[0005]FIG. 1 is a cross-sectional view of a conventional channelion-implantation used to adjust V_(T). A p-type dopant can beion-implanted into an entire p-type integrated circuit substrate 10,including a isolation region 12, to form a doping region 20 withoutusing an ion-implantation mask. Thereafter, a gate electrode 24 and ann-type source/drain region 26 can be formed.

[0006] When the channel ion-implantation is performed throughout theentire substrate 10, as shown in FIG. 1, the source/drain region 26 canbe influenced by the doping region 20 formed by the channelion-implantation. In this case, when the doping concentration isincreased during the channel ion-implantation to prevent a short channeleffect, substrate defects may occur between the isolation region 12 andthe source/drain region 26 or in a depletion region.

[0007] Since the dopant implanted during the channel ion-implantationmay have a polarity that is opposite a dopant that is ion-implanted intothe source/drain region, an electric field at the pn junction boundarymay be increased, thereby increasing junction leakage current.Consequently, data retention time may be decreased. Moreover, channelion-implantation performed at a high concentration may increase junctioncapacitance. As a result, when charge stored in the capacitors of memorycells is read, the information may be affected by noise, so that asensing margin is decreased.

[0008]FIGS. 2A and 2B are cross-sectional views that illustrateconventional channel ion-implantation to adjust V_(T). A doping region50 can be formed by implanting a p-type dopant 46 into only a regionwhere a gate electrode 54 will be formed on an integrated circuitsubstrate 40, using a reverse gate pattern 44, formed of a photoresistfilm, as an ion-implantation mask. Thereafter, the gate electrode 54 canbe formed on the doping region 50.

[0009] According to some conventional methods described with referenceto FIGS. 2A and 2B, as the integration density of devices increases, itmay become difficult to form the reverse gate pattern 44 used as achannel ion-implantation mask. In addition, when conventional methodsare applied to the manufacturing of devices having a small pitch betweengate electrodes 54, various problems can be caused by the misalignmentof the mask or by variation in the critical dimension in a channelion-implantation step or a gate electrode-patterning step followed bythe channel ion-implantation step. For example, when the reverse gatepattern 44 is misaligned, the doping region 50 formed at the edge of anisolation region 42 may be affected by the junction leakage current.Accordingly, the operation of a device may be adversely affected.

[0010] In other conventional methods, channel ion-implantation can beperformed using a reverse gate pattern as shown in FIG. 2A, and then agate electrode may be formed to be self-aligned to the reverse gatepattern. However, in this method it may be difficult to form thestructure of a gate electrode having multiple layers. In addition,processes of forming self-aligned contacts, such as a landing padself-aligned with respect to a gate electrode may be impracticable.

SUMMARY OF THE INVENTION

[0011] Embodiments of methods according to the present invention mayallow a channel region to be formed between isolation regions of anintegrated circuit substrate. Pursuant to these embodiments, a mask canbe formed on an isolation region that extends onto a portion of thesubstrate adjacent to the isolation region to provide a shielded portionof the substrate adjacent to the isolation region and an exposed portionof the substrate spaced apart from the isolation region having theshielded portion therebetween. A channel region can be formed in theexposed portion of the substrate.

[0012] In some embodiments according to the present invention, a firstlevel of ions can be implanted in the shielded region adjacent to theisolation region. A second level of ions can be implanted in the channelregion spaced apart from the isolation region, wherein the second levelis greater than the first level.

[0013] In some embodiments according to the present invention, boronions are implanted in the exposed region and then boron difluoride ionsare implanted in the exposed region. In some embodiments according tothe present invention, a gate electrode can be formed on the channelregion and a contact can be formed on the shielded region. Source anddrain regions can be formed in the channel region self aligned to thegate electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIGS. 1, 2A and 2B are a cross-sectional views that illustrateconventional methods of forming channel regions in integrated circuitmemory devices using ion implantation.

[0015]FIGS. 3A through 8 are diagrams that illustrate embodiments ofmethods for forming channel regions in integrated circuits andintegrated circuit according to the present invention.

[0016]FIG. 9 is a graph that illustrates electrical characteristics ofintegrated circuits formed using embodiments of methods according to thepresent invention and conventional integrated circuits.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0017] The present invention now will be described more fullyhereinafter with reference to the accompanying drawings, in whichpreferred embodiments of the invention are shown. This invention may,however, be embodied in many different forms and should not be construedas limited to the embodiments set forth herein; rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the invention to thoseskilled in the art. In the drawings, the thickness of layers and regionsare exaggerated for clarity. It will be understood that when an elementsuch as a layer, region or substrate is referred to as being “on”another element, it can be directly on the other element or interveningelements may also be present. Like numbers refer to like elementsthroughout.

[0018]FIG. 3A is a top view of a integrated circuit substrate 100 inwhich an isolation region 102 is formed using a trench isolation method.FIG. 3B is a cross-sectional view of FIG. 3A taken along the lineIII-III′. As shown in FIGS. 3A and 3B, a well (not shown) and a channelstop layer 106 are formed in the integrated circuit substrate 100 usingan ion-implantation method in which an active region 104 is defined bythe isolation region 102. The active region 104 includes two portions104 a that are spaced apart from one another and on which gateelectrodes can be subsequently formed. The active region 104 alsoincludes two portions 104 c each located between respective ones of theportions 104 a and the isolation region 102 adjacent thereto and onwhich storage node contacts of a capacitor can be subsequently formed.The active region 104 further includes a portion 104 b between the twoportions 104 a on which a bit line contact can be subsequently formed.

[0019]FIG. 4A is a top view of the integrated circuit substrate 100including the isolation region 102 therein and having a channelion-implantation mask 110 thereon. FIG. 4B is a cross-sectional view ofFIG. 4A taken along the line IV-IV′. As shown in FIGS. 4A and 4B, themask pattern 110 is formed on the isolation region 102 and extends ontoa portion of the substrate 100 adjacent to the isolation region 102 toshield the portions 104 c of the substrate 100 adjacent to the isolationregion. In some embodiments, the shielded portions 104 c of thesubstrate 100 extend about 0.4 mm microns beyond the isolation region102 and may be controlled with a range of about 0.1 mm to 0.18 mm.

[0020] The mask pattern 110 also includes an opening 112 that exposesthe portions 104 a and 104 b of the active region 104. The mask pattern110 can be formed to completely shield the entire portion 104 c. Themask pattern 110 can be formed, for example, of a photoresist film.

[0021] Referring to FIG. 5, a p-type dopant 120 is implanted into theintegrated circuit substrate 100 using the mask pattern 110 as anion-implantation mask, thereby forming a channel region 122 in theportions 104 a and 104 b of the active region 104. The p-type dopant 120may be formed of boron ions or boron difluoride ions. The channelimplantation may be performed two or more times to form the channelregion 122. For example, a first channel ion-implantation can beperformed using boron ions and a second local channel ion-implantationprocess can be performed thereafter using boron difluoride ions to formthe channel ion-implantation region 122. In some embodiments of ionimplantation according to the present invention, ion energies and ionimplantation concentrations per unit area may be controlled. Thesubstrate may have different ion concentration distributions dependingon the depth of the substrate after an ion implantation process.Further, the ion concentration distributions in the substrate may bechanged after a subsequent heat treatment. Thus, the level of ionconcentration can be known accurately for the dimension ions/cm², andcan be estimated for the dimension ions/cm³. In some embodiment of thepresent invention, the first and second levels of ion concentrationsresulting from a channel ion implantation can be about 1×10¹⁷ ions/cm³.The first and second levels of ion concentrations can be about 5×10¹² to15×10¹² ions/cm².

[0022] Referring to FIG. 6, the mask pattern 110 is removed, and a gateelectrode 130 is formed on the portion 104 a. A silicon nitride filmpattern 132, which can be used as an etching mask to form the gateelectrode 130, can remain on the upper surface of the gate electrode130.

[0023] Referring to FIG. 7, a nitride spacer 134 is formed on thesidewalls of the gate electrode 130 and the silicon nitride film pattern132. Thereafter, an n-type dopant 140 is ion-implanted into theintegrated circuit substrate 100 to form source/drain regions 142 a and142 b in the portions 104 b and 104 c, respectively. It will beunderstood by those having skill in the art that the source/drainregions 142 a and 142 b can be formed to have a lightly doped drain(LDD) structure.

[0024] A contact plug for connecting the source/drain region 142 a to abit line is formed on the source/drain region 142 a, and a contact plugfor connecting the source/drain region 142 b to a storage node of acapacitor is formed on the source/drain region 142 b. As illustrated inFIG. 5, the channel region 122 is positioned below the two gateelectrodes 130 and a bit line contact, which is formed in the portion104 b between the two gate electrodes 130, but is not positioned below astorage node contact of a capacitor formed in the portion 104 c.Accordingly, the effect of the channel ion-implantation on thesource/drain region 142 b may be reduced. Therefore, damage from thechannel ion-implantation (and/or an increase in junction leakage currentor junction capacitance) due to an increase in an electric field can beprevented, thereby increasing data retention time. Junction leakagecurrent may be produced in the source/drain region 142 a below the bitline contact due to the effect of the channel ion-implantation region122, but the effects of such leakage current can be ignored.

[0025] Referring to FIG. 8, a contact plug 150 a is formed on theportion 104 b to connect to the source/drain region 142 a, and a contactplug 150 b is formed on the portion 104 c to be connected to thesource/drain region 142 b. Each of the contact plugs 150 a and 150 b isformed self-aligned to each gate electrode 130. The contact plug 150 aconnects the source/drain region 142 a to a bit line, and the contactplug 150 b connects the source/drain region 142 b to a storage node of acapacitor.

[0026] As described above, according to embodiments of methods offorming integrated circuits, the source/drain region 142 b may not beinfluenced by channel ion-implantation used to adjust V_(T) of atransistor to a proper level, thereby decreasing junction leakagecurrent. Consequently, sheet resistance at a junction area can bedecreased so that the saturation current of a transistor can beincreased. In addition, junction capacitance can be decreased so thatthe floating capacitance of the bit line can be decreased.

[0027]FIG. 9 is a graph illustrates the electrical characteristics ofintegrated circuit memory devices formed using embodiments of methodsaccording to the present invention. An integrated circuit memory deviceaccording to the present invention, as shown in FIG. 8, was used toobtain the estimated results shown in FIG. 9.

[0028] During channel ion-implantation, boron ions were implanted into aportion over which a gate electrode would be formed and into a portionwhere a source/drain region connected to a bit line contact would beformed in an active region at a dose of about 1.0E13/cm² and withion-implantation energy of about 30 KeV in a first localion-implantation step. Then boron difluoride ions were implanted intothe portion over which the gate electrode would be formed and theportion where the source/drain region connected to the bit line contactwould be formed in the active region at a dose of about 1.2E13/cm² andwith ion-implantation energy of about 30 KeV in a second localion-implantation process. This case is represented by—in the graph ofFIG. 9. In another case, dual channel ion-implantation was performedunder the same conditions as the above case, but channelion-implantation was performed on an entire active region as in theprior art described in FIG. 1. This case is represented by—in the graphof FIG. 9. The two cases are represented by the numbers of accumulatedfailed cells according to refresh time.

[0029] In addition, during channel ion-implantation, boron ions wereimplanted into a portion over which a gate electrode would be formed andinto a portion where a source/drain region connected to a bit linecontact would be formed in an active region at a dose of about1.0E13/cm² and with ion-implantation energy of about 30 KeV in a firstlocal ion-implantation step, and then boron difluoride ions wereimplanted into only the portion over which the gate electrode would beformed and the portion where the source/drain region connecting to thebit line contact would be formed in the active region at a dose of about1.5E13/cm² and with ion-implantation energy of about 30 KeV in a secondlocal ion-implantation process. This case is represented by -∇- in thegraph of FIG. 9. In another case, dual channel ion-implantation wasperformed under the same conditions as the above case, but the channelion-implantation was performed on an entire active region as in theprior art described in FIG. 1. This case is represented by—in the graphof FIG. 9. The two cases are represented by the numbers of accumulatedfailed cells according to refresh time.

[0030] As shown in FIG. 9, the number of failed cells in an integratedcircuit memory device manufactured by local channel ion-implantation onan active region according to the present invention can be reduced byabout 20-30% compared to a integrated circuit memory device formed usingconventional channel ion-implantation throughout an active regionaccording to a conventional method.

[0031] In embodiments of methods of forming integrated circuit memorydevices according to the present invention, a mask pattern can be formedto include an opening which exposes a portion of the substrate where agate electrode is formed and a portion where a source/drain regionconnected to a bit line contact is formed in an active region of aintegrated circuit substrate. Ions can be implanted through the mask toadjust V_(T) of a cell transistor to a proper level. A source/drainregion connected to a storage node contact of a capacitor, may not beaffected by the channel ion-implantation. As a result, damage to asubstrate or an increase in junction leakage current due to an increasein an electric field can be reduced near a source/drain region connectedto a storage node contact. In addition, sheet resistance in a junctionarea can be reduced, thereby increasing the saturation current of a celltransistor, and junction capacitance can be reduced, thereby decreasingthe floating capacitance of a bit line.

[0032] In the drawings and specification, there have been disclosedtypical preferred embodiments of the invention and, although specificterms are employed, they are used in a generic and descriptive senseonly and not for purposes of limitation, the scope of the inventionbeing set forth in the following claims.

What is claimed:
 1. An integrated circuit comprising: a substrate havingan isolation region therein; a channel region in the substrate having afirst portion adjacent to the isolation region having a first level ofions therein and having a second portion spaced apart from the isolationregion and having the first portion therebetween, the second portionhaving a second level of ions therein.
 2. An integrated circuitaccording to claim 5 further comprising: a gate electrode on the secondportion; a contact on the first portion; and source and drain regions onthe channel region self aligned to the gate electrode.